NXP LPC LWIP port documentation  v1.10
LWIP port for LPC devices
C:/dev/git/lwip_work/lpc43xx/lwip_lpc/nxpcommon/arch/lpc18xx_43xx/lpc18xx_43xx_mac_regs.h
00001 /**********************************************************************
00002 * $Id$    lpc43xx_mac.h     2011-06-02
00003 */
00032 #ifndef __lpc18xx_lpc43xx_mac_regs_H_
00033 #define __lpc18xx_lpc43xx_mac_regs_H_
00034 
00035 #ifdef LPC43XX
00036 #include "lpc43xx.h"
00037 #else
00038 #ifdef LPC43XX
00039 #include "lpc18xx.h"
00040 #else
00041 #error LPC18XX or LPC43XX for target system not defined!
00042 #endif
00043 #endif
00044 
00045 #include "lpc_types.h"
00046 
00047 #ifdef __cplusplus
00048 extern "C"
00049 {
00050 #endif
00051 
00062 /* MAC_CONFIG register bit defines */
00063 #define MAC_CFG_RE     (1 << 2)      
00064 #define MAC_CFG_TE     (1 << 3)      
00065 #define MAC_CFG_DF     (1 << 4)      
00066 #define MAC_CFG_BL(n)  ((n) << 5)    
00067 #define MAC_CFG_ACS    (1 << 7)      
00068 #define MAC_CFG_LUD    (1 << 8)      
00069 #define MAC_CFG_DR     (1 << 9)      
00070 #define MAC_CFG_IPC    (1 << 10)     
00071 #define MAC_CFG_DM     (1 << 11)     
00072 #define MAC_CFG_LM     (1 << 12)     
00073 #define MAC_CFG_DO     (1 << 13)     
00074 #define MAC_CFG_FES    (1 << 14)     
00075 #define MAC_CFG_PS     (1 << 15)     
00076 #define MAC_CFG_DCRS   (1 << 16)     
00077 #define MAC_CFG_IFG(n) ((n) << 17)   
00078 #define MAC_CFG_JE     (1 << 20)     
00079 #define MAC_CFG_JD     (1 << 22)     
00080 #define MAC_CFG_WD     (1 << 23)     
00082 /* MAC_FRAME_FILTER register bit defines */
00083 #define MAC_FF_PR      (1 << 0)      
00084 #define MAC_FF_DAIF    (1 << 3)      
00085 #define MAC_FF_PM      (1 << 4)      
00086 #define MAC_FF_DBF     (1 << 5)      
00087 #define MAC_FF_PCF(n)  ((n) << 6)    
00088 #define MAC_FF_SAIF    (1 << 8)      
00089 #define MAC_FF_SAF     (1 << 9)      
00090 #define MAC_FF_RA      (1UL << 31)   
00092 /* MAC_MII_ADDR register bit defines */
00093 #define MAC_MIIA_GB    (1 << 0)      
00094 #define MAC_MIIA_W     (1 << 1)      
00095 #define MAC_MIIA_CR(n) ((n) << 2)    
00096 #define MAC_MIIA_GR(n) ((n) << 6)    
00097 #define MAC_MIIA_PA(n) ((n) << 11)   
00099 /* MAC_MII_DATA register bit defines */
00100 #define MAC_MIID_GDMSK (0xFFFF)      
00102 /* MAC_FLOW_CONTROL register bit defines */
00103 #define MAC_FC_FCB     (1 << 0)      
00104 #define MAC_FC_TFE     (1 << 1)      
00105 #define MAC_FC_RFE     (1 << 2)      
00106 #define MAC_FC_UP      (1 << 3)      
00107 #define MAC_FC_PLT(n)  ((n) << 4)    
00108 #define MAC_FC_DZPQ    (1 << 7)      
00109 #define MAC_FC_PT(n)   ((n) << 16)   
00111 /* MAC_VLAN_TAG register bit defines */
00112 #define MAC_VT_VL(n)   ((n) << 0)    
00113 #define MAC_VT_ETC     (1 << 7)      
00115 /* MAC_DEBUG register bit defines */
00116 
00117 /* MAC_PMT_CTRL_STAT register bit defines */
00118 #define MAC_PMT_PD     (1 << 0)      
00119 #define MAC_PMT_MPE    (1 << 1)      
00120 #define MAC_PMT_WFE    (1 << 2)      
00121 #define MAC_PMT_MPR    (1 << 5)      
00122 #define MAC_PMT_WFR    (1 << 6)      
00123 #define MAC_PMT_GU     (1 << 9)      
00124 #define MAC_PMT_WFFRPR (1UL << 31)   
00126 /* MAC_INTR_MASK register bit defines */
00127 #define MAC_IM_PMT     (1 << 3)      
00129 /* MAC_ADDR0_HIGH register bit defines */
00130 #define MAC_ADRH_MO    (1UL << 31)   
00132 /* MAC_ADDR0_HIGH register bit defines */
00133 #define MAC_ADRH_MO    (1UL << 31)   
00135 /* MAC_TIMESTAMP register bit defines */
00136 #define MAC_TS_TSENA   (1 << 0)      
00137 #define MAC_TS_TSCFUP  (1 << 1)      
00138 #define MAC_TS_TSINIT  (1 << 2)      
00139 #define MAC_TS_TSUPDT  (1 << 3)      
00140 #define MAC_TS_TSTRIG  (1 << 4)      
00141 #define MAC_TS_TSADDR  (1 << 5)      
00142 #define MAC_TS_TSENAL  (1 << 8)      
00143 #define MAC_TS_TSCTRL  (1 << 9)      
00144 #define MAC_TS_TSVER2  (1 << 10)     
00145 #define MAC_TS_TSIPENA (1 << 11)     
00146 #define MAC_TS_TSIPV6E (1 << 12)     
00147 #define MAC_TS_TSIPV4E (1 << 13)     
00148 #define MAC_TS_TSEVNT  (1 << 14)     
00149 #define MAC_TS_TSMSTR  (1 << 15)     
00150 #define MAC_TS_TSCLKT(n) ((n) << 16) 
00151 #define MAC_TS_TSENMA  (1 << 18)     
00153 /* DMA_BUS_MODE register bit defines */
00154 #define DMA_BM_SWR     (1 << 0)      
00155 #define DMA_BM_DA      (1 << 1)      
00156 #define DMA_BM_DSL(n)  ((n) << 2)    
00157 #define DMA_BM_ATDS    (1 << 7)      
00158 #define DMA_BM_PBL(n)  ((n) << 8)    
00159 #define DMA_BM_PR(n)   ((n) << 14)   
00160 #define DMA_BM_FB      (1 << 16)     
00161 #define DMA_BM_RPBL(n) ((n) << 17)   
00162 #define DMA_BM_USP     (1 << 23)     
00163 #define DMA_BM_PBL8X   (1 << 24)     
00164 #define DMA_BM_AAL     (1 << 25)     
00165 #define DMA_BM_MB      (1 << 26)     
00166 #define DMA_BM_TXPR    (1 << 27)     
00168 /* DMA_STAT register bit defines */
00169 #define DMA_ST_TI      (1 << 0)      
00170 #define DMA_ST_TPS     (1 << 1)      
00171 #define DMA_ST_TU      (1 << 2)      
00172 #define DMA_ST_TJT     (1 << 3)      
00173 #define DMA_ST_OVF     (1 << 4)      
00174 #define DMA_ST_UNF     (1 << 5)      
00175 #define DMA_ST_RI      (1 << 6)      
00176 #define DMA_ST_RU      (1 << 7)      
00177 #define DMA_ST_RPS     (1 << 8)      
00178 #define DMA_ST_RWT     (1 << 9)      
00179 #define DMA_ST_ETI     (1 << 10)     
00180 #define DMA_ST_FBI     (1 << 13)     
00181 #define DMA_ST_ERI     (1 << 14)     
00182 #define DMA_ST_AIE     (1 << 15)     
00183 #define DMA_ST_NIS     (1 << 16)     
00184 #define DMA_ST_ALL     (0x1E7FF)     
00186 /* DMA_OP_MODE register bit defines */
00187 #define DMA_OM_SR      (1 << 1)      
00188 #define DMA_OM_OSF     (1 << 2)      
00189 #define DMA_OM_RTC(n)  ((n) << 3)    
00190 #define DMA_OM_FUF     (1 << 6)      
00191 #define DMA_OM_FEF     (1 << 7)      
00192 #define DMA_OM_ST      (1 << 13)     
00193 #define DMA_OM_TTC(n)  ((n) << 14)   
00194 #define DMA_OM_FTF     (1 << 20)     
00195 #define DMA_OM_TSF     (1 << 21)     
00196 #define DMA_OM_DFF     (1 << 24)     
00197 #define DMA_OM_RSF     (1 << 25)     
00198 #define DMA_OM_DT      (1 << 26)     
00200 /* DMA_INT_EN register bit defines */
00201 #define DMA_IE_TIE     (1 << 0)      
00202 #define DMA_IE_TSE     (1 << 1)      
00203 #define DMA_IE_TUE     (1 << 2)      
00204 #define DMA_IE_TJE     (1 << 3)      
00205 #define DMA_IE_OVE     (1 << 4)      
00206 #define DMA_IE_UNE     (1 << 5)      
00207 #define DMA_IE_RIE     (1 << 6)      
00208 #define DMA_IE_RUE     (1 << 7)      
00209 #define DMA_IE_RSE     (1 << 8)      
00210 #define DMA_IE_RWE     (1 << 9)      
00211 #define DMA_IE_ETE     (1 << 10)     
00212 #define DMA_IE_FBE     (1 << 13)     
00213 #define DMA_IE_ERE     (1 << 14)     
00214 #define DMA_IE_AIE     (1 << 15)     
00215 #define DMA_IE_NIE     (1 << 16)     
00217 /* DMA_MFRM_BUFOF register bit defines */
00218 #define DMA_MFRM_FMCMSK (0xFFFF)     
00219 #define DMA_MFRM_OC    (1 << 16)     
00220 #define DMA_MFRM_FMA(n) (((n) & 0x0FFE0000) >> 17) 
00221 #define DMA_MFRM_OF    (1 << 28)     
00223 /* Common TRAN_DESC_T and TRAN_DESC_ENH_T CTRLSTAT field bit defines */
00224 #define TDES_DB        (1 << 0)      
00225 #define TDES_UF        (1 << 1)      
00226 #define TDES_ED        (1 << 2)      
00227 #define TDES_CCMSK(n)  (((n) & 0x000000F0) >> 3) 
00228 #define TDES_VF        (1 << 7)      
00229 #define TDES_EC        (1 << 8)      
00230 #define TDES_LC        (1 << 9)      
00231 #define TDES_NC        (1 << 10)     
00232 #define TDES_LCAR      (1 << 11)     
00233 #define TDES_IPE       (1 << 12)     
00234 #define TDES_FF        (1 << 13)     
00235 #define TDES_JT        (1 << 14)     
00236 #define TDES_ES        (1 << 15)     
00237 #define TDES_IHE       (1 << 16)     
00238 #define TDES_TTSS      (1 << 17)     
00239 #define TDES_OWN       (1UL << 31)   
00241 /* TRAN_DESC_ENH_T only CTRLSTAT field bit defines */
00242 #define TDES_ENH_IC   (1UL << 30)    
00243 #define TDES_ENH_LS   (1 << 29)      
00244 #define TDES_ENH_FS   (1 << 28)      
00245 #define TDES_ENH_DC   (1 << 27)      
00246 #define TDES_ENH_DP   (1 << 26)      
00247 #define TDES_ENH_TTSE (1 << 25)      
00248 #define TDES_ENH_CIC(n) ((n) << 22)  
00249 #define TDES_ENH_TER  (1 << 21)      
00250 #define TDES_ENH_TCH  (1 << 20)      
00252 /* TRAN_DESC_T only BSIZE field bit defines */
00253 #define TDES_NORM_IC   (1UL << 31)   
00254 #define TDES_NORM_FS   (1 << 30)     
00255 #define TDES_NORM_LS   (1 << 29)     
00256 #define TDES_NORM_CIC(n) ((n) << 27) 
00257 #define TDES_NORM_DC   (1 << 26)     
00258 #define TDES_NORM_TER  (1 << 25)     
00259 #define TDES_NORM_TCH  (1 << 24)     
00260 #define TDES_NORM_DP   (1 << 23)     
00261 #define TDES_NORM_TTSE (1 << 22)     
00262 #define TDES_NORM_BS2(n) (((n) & 0x3FF) << 11) 
00263 #define TDES_NORM_BS1(n) (((n) & 0x3FF) << 0) 
00265 /* TRAN_DESC_ENH_T only BSIZE field bit defines */
00266 #define TDES_ENH_BS2(n) (((n) & 0xFFF) << 16) 
00267 #define TDES_ENH_BS1(n) (((n) & 0xFFF) << 0) 
00269 /* Common REC_DESC_T and REC_DESC_ENH_T STATUS field bit defines */
00270 #define RDES_ESA      (1 << 0)       
00271 #define RDES_CE       (1 << 1)       
00272 #define RDES_DE       (1 << 2)       
00273 #define RDES_RE       (1 << 3)       
00274 #define RDES_RWT      (1 << 4)       
00275 #define RDES_FT       (1 << 5)       
00276 #define RDES_LC       (1 << 6)       
00277 #define RDES_TSA      (1 << 7)       
00278 #define RDES_LS       (1 << 8)       
00279 #define RDES_FS       (1 << 9)       
00280 #define RDES_VLAN     (1 << 10)      
00281 #define RDES_OE       (1 << 11)      
00282 #define RDES_LE       (1 << 12)      
00283 #define RDES_SAF      (1 << 13)      
00284 #define RDES_DE       (1 << 14)      
00285 #define RDES_ES       (1 << 15)      
00286 #define RDES_FLMSK(n) (((n) & 0x3FFF0000) >> 16) 
00287 #define RDES_AFM      (1 << 30)      
00288 #define RDES_OWN      (1UL << 31)    
00290 /* Common REC_DESC_T and REC_DESC_ENH_T CTRL field bit defines */
00291 #define RDES_DINT     (1UL << 31)    
00293 /* REC_DESC_T pnly CTRL field bit defines */
00294 #define RDES_NORM_RER (1 << 25)      
00295 #define RDES_NORM_RCH (1 << 24)      
00296 #define RDES_NORM_BS2(n) (((n) & 0x3FF) << 11) 
00297 #define RDES_NORM_BS1(n) (((n) & 0x3FF) << 0) 
00299 /* REC_DESC_ENH_T only CTRL field bit defines */
00300 #define RDES_ENH_RER  (1 << 15)      
00301 #define RDES_ENH_RCH  (1 << 14)      
00302 #define RDES_ENH_BS2(n) (((n) & 0xFFF) << 16) 
00303 #define RDES_ENH_BS1(n) (((n) & 0xFFF) << 0) 
00305 /* REC_DESC_ENH_T only EXTSTAT field bit defines */
00306 #define RDES_ENH_IPPL(n)  (((n) & 0x7) >> 2) 
00307 #define RDES_ENH_IPHE     (1 << 3)   
00308 #define RDES_ENH_IPPLE    (1 << 4)   
00309 #define RDES_ENH_IPCSB    (1 << 5)   
00310 #define RDES_ENH_IPV4     (1 << 6)   
00311 #define RDES_ENH_IPV6     (1 << 7)   
00312 #define RDES_ENH_MTMSK(n) (((n) & 0xF) >> 8) 
00314 /* Maximum size of an ethernet buffer */
00315 #define EMAC_ETH_MAX_FLEN (1536)
00316 
00317 /* Structure of a transmit descriptor (without timestamp) */
00318 typedef struct
00319 {
00320   __IO uint32_t CTRLSTAT;            
00321   __IO uint32_t BSIZE;               
00322   __IO uint32_t B1ADD;               
00323   __IO uint32_t B2ADD;               
00324 } TRAN_DESC_T;
00325 
00326 /* Structure of a enhanced transmit descriptor (with timestamp) */
00327 typedef struct
00328 {
00329   __IO uint32_t CTRLSTAT;            
00330   __IO uint32_t BSIZE;               
00331   __IO uint32_t B1ADD;               
00332   __IO uint32_t B2ADD;               
00333   __IO uint32_t TDES4;               
00334   __IO uint32_t TDES5;               
00335   __IO uint32_t TTSL;                
00336   __IO uint32_t TTSH;                
00337 } TRAN_DESC_ENH_T;
00338 
00339 /* Structure of a receive descriptor (without timestamp) */
00340 typedef struct
00341 {
00342   __IO uint32_t STATUS;              
00343   __IO uint32_t CTRL;                
00344   __IO uint32_t B1ADD;               
00345   __IO uint32_t B2ADD;               
00346 } REC_DESC_T;
00347 
00348 /* Structure of a enhanced receive descriptor (with timestamp) */
00349 typedef struct
00350 {
00351   __IO uint32_t STATUS;              
00352   __IO uint32_t CTRL;                
00353   __IO uint32_t B1ADD;               
00354   __IO uint32_t B2ADD;               
00355   __IO uint32_t EXTSTAT;             
00356   __IO uint32_t RDES5;               
00357   __IO uint32_t RTSL;                
00358   __IO uint32_t RTSH;                
00359 } REC_DESC_ENH_T;
00360 
00365 #ifdef __cplusplus
00366 }
00367 #endif
00368 
00369 #endif /* __lpc18xx_lpc43xx_mac_regs_H_ */