|Registers / WWDT Register description|
The WDWARNINT register determines the watchdog timer counter value that will generate a watchdog interrupt. When the watchdog timer counter matches the value defined by WARNINT, an interrupt will be generated after the subsequent WDCLK.
A match of the watchdog timer counter to WARNINT occurs when the bottom 10 bits of the counter have the same value as the 10 bits of WARNINT, and the remaining upper bits of the counter are all 0. This gives a maximum time of 1,023 watchdog timer counts (4,096 watchdog clocks) for the interrupt to occur prior to a watchdog event. If WARNINT is 0, the interrupt will occur at the same time as the watchdog event.
|9:0||WARNINT||Watchdog warning interrupt compare value.||0|
|31:10||-||Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.||NA|
© NXP N.V. 2014. All rights reserved.