WWDT MOD addressOffset = 0x000

The WDMOD register controls the operation of the Watchdog. Note that a watchdog feed must be performed before any changes to the WDMOD register take effect.

Table 1. WWDT registerName = MOD addressOffset = 0x000
Bit Symbol Value Description Reset value
0 WDEN   Watchdog enable bit. Once this bit has been written with a 1, it cannot be re-written with a 0. Once this bit is set to one, the watchdog timer starts running after a watchdog feed. 0
    0 The watchdog timer is stopped.  
    1 The watchdog timer is running.  
1 WDRESET   Watchdog reset enable bit. Once this bit has been written with a 1 it cannot be re-written with a 0. 0
    0 A watchdog time-out will not cause a chip reset.  
    1 A watchdog time-out will cause a chip reset.  
2 WDTOF   Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT. Cleared by software. Causes a chip reset if WDRESET = 1. 0 (only after external reset)
3 WDINT   Warning interrupt flag. Set when the timer reaches the value in WDWARNINT. Cleared by software. 0
4 WDPROTECT   Watchdog update mode. This bit can be set once by software and is only cleared by a reset. 0
    0 The watchdog time-out value (TC) can be changed at any time.  
    1 The watchdog time-out value (TC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW.  
5 LOCK   A 1 in this bit prevents disabling or powering down the watchdog oscillator. This bit can be set once by software and is only cleared by any reset. 0
31:6 -   Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA

Once the WDEN, WDPROTECT, or WDRESET bits are set they can not be cleared by software. Both flags are cleared by an external reset or a Watchdog timer reset.

WDTOF The Watchdog time-out flag is set when the Watchdog times out, when a feed error occurs, or when PROTECT =1 and an attempt is made to write to the TC register. This flag is cleared by software writing a 0 to this bit.

WDINT The Watchdog interrupt flag is set when the Watchdog counter reaches the value specified by WARNINT. This flag is cleared when any reset occurs, and is cleared by software by writing a 0 to this bit.

In all power modes except Deep power-down mode, a Watchdog reset or interrupt can occur when the watchdog is running and has an operating clock source. The watchdog oscillator can be configured to keep running in Sleep, Deep-sleep modes, and Power-down modes.

If a watchdog interrupt occurs in Sleep, Deep-sleep mode, or Power-down mode, and the WWDT interrupt is enabled in the NVIC, the device will wake up. Note that in Deep-sleep and Power-down modes, the WWDT interrupt must be enabled in the STARTERP1 register in addition to the NVIC.

See the following registers:

SYSCON registerName = STARTERP1 addressOffset = 0x214

Table 2. WWDT Watchdog operating modes selection
WDEN WDRESET Mode of Operation
0 X (0 or 1) Debug/Operate without the Watchdog running.
1 0 Watchdog interrupt mode: the watchdog warning interrupt will be generated but watchdog reset will not.

When this mode is selected, the watchdog counter reaching the value specified by WDWARNINT will set the WDINT flag and the Watchdog interrupt request will be generated.

1 1 Watchdog reset mode: both the watchdog interrupt and watchdog reset are enabled.

When this mode is selected, the watchdog counter reaching the value specified by WDWARNINT will set the WDINT flag and the Watchdog interrupt request will be generated, and the watchdog counter reaching zero will reset the microcontroller. A watchdog feed prior to reaching the value of WDWINDOW will also cause a watchdog reset.


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