WWDT Features

  • Internally resets chip if not reloaded during the programmable time-out period.
  • Optional windowed operation requires reload to occur between a minimum and maximum time-out period, both programmable.
  • Optional warning interrupt can be generated at a programmable time prior to watchdog time-out.
  • Programmable 24-bit timer with internal fixed pre-scaler.
  • Selectable time period from 1,024 watchdog clocks (T _ WDCLK × 256  × 4) to over 67 million watchdog clocks (T_ WDCLK × 2 ^ 24 × 4) in increments of 4 watchdog clocks.
  • “Safe” watchdog operation. Once enabled, requires a hardware reset or a Watchdog reset to be disabled.
  • Incorrect feed sequence causes immediate watchdog event if enabled.
  • The watchdog reload value can optionally be protected such that it can only be changed after the “warning interrupt” time is reached.
  • Flag to indicate Watchdog reset.
  • The Watchdog clock (WDCLK) source is the WatchDog oscillator.
  • The Watchdog timer can be configured to run in Deep-sleep or Power-down mode.
  • Debug mode.

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