|Registers / USART0/1/2 Register description|
The STAT register primarily provides a complete set of USART status flags for software to read. Flags other than read-only flags may be cleared by writing ones to corresponding bits of STAT. Interrupt status flags that are read-only and cannot be cleared by software, can be masked using the INTENCLR register (see USART registerName = INTENCLR addressOffset = 0x010).
The error flags for received noise, parity error, framing error, and overrun are set immediately upon detection and remain set until cleared by software action in STAT.
|0||RXRDY||Receiver Ready flag. When 1, indicates that data is available to be read from the receiver buffer. Cleared after a read of the RXDAT or RXDATSTAT registers.||0||RO|
|1||RXIDLE||Receiver Idle. When 0, indicates that the receiver is currently in the process of receiving data. When 1, indicates that the receiver is not currently in the process of receiving data.||1||RO|
|2||TXRDY||Transmitter Ready flag. When 1, this bit indicates that data may be written to the transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data is written to TXDAT. Set when the data is moved from the transmit buffer to the transmit shift register.||1||RO|
|3||TXIDLE||Transmitter Idle. When 0, indicates that the transmitter is currently in the process of sending data.When 1, indicate that the transmitter is not currently in the process of sending data.||1||RO|
|4||CTS||This bit reflects the current state of the CTS signal, regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled.||NA||RO|
|5||DELTACTS||This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software.||0||W1|
Transmitter Disabled Interrupt flag. When 1, this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS in the CFG register (TXDIS = 1).
|7||-||Reserved. Read value is undefined, only zero should be written.||NA||NA|
|8||OVERRUNINT||Overrun Error interrupt flag. This flag is set when a new character is received while the receiver buffer is still in use. If this occurs, the newly received character in the shift register is lost.||0||W1|
|9||-||Reserved. Read value is undefined, only zero should be written.||NA||NA|
|10||RXBRK||Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the character would be missing. RXBRK is cleared when the Un_RXD pin goes high.||0||RO|
|11||DELTARXBRK||This bit is set when a change in the state of receiver break detection occurs. Cleared by software.||0||W1|
|12||START||This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software.||0||W1|
|13||FRAMERRINT||Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source.||0||W1|
|14||PARITYERRINT||Parity Error interrupt flag. This flag is set when a parity error is detected in a received character..||0||W1|
|15||RXNOISEINT||Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit, except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a received data bit contains one disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or loss of synchronization during data reception.||0||W1|
|31:16||-||Reserved. Read value is undefined, only zero should be written.||NA||NA|
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