USART CTL addressOffset = 0x004

The CTL register controls aspects of USART operation that are more likely to change during operation.

Table 1. USART registerName = CTL addressOffset = 0x004
Bit Symbol Value Description Reset Value
0 -   Reserved. Read value is undefined, only zero should be written. NA
1 TXBRKEN   Break Enable. 0
    0 Normal operation.  
    1 Continuous break is sent immediately when this bit is set, and remains until this bit is cleared.

A break may be sent without danger of corrupting any currently transmitting character if the transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled (TXDISINT in STAT = 1) before writing 1 to TXBRKEN.

 
2 ADDRDET   Enable address detect mode. 0
    0 Disabled. The USART presents all incoming data.  
    1 Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally, generating a received data interrupt. Software can then check the data to see if this is an address that should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled normally.  
5:3 -   Reserved. Read value is undefined, only zero should be written. NA
6 TXDIS   Transmit Disable. 0
    0 Not disabled. USART transmitter is not disabled.  
    1 Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This feature can be used to facilitate software flow control.  
7 -   Reserved. Read value is undefined, only zero should be written. NA
8 CC   Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode. 0
    0 Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to complete a character that is being received.  
    1 Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on Un_RxD independently from transmission on Un_TXD).  
9 CLRCC   Clear Continuous Clock. 0
    0 No affect on the CC bit.  
    1 Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is cleared at the same time.  
31:10 -   Reserved. Read value is undefined, only zero should be written. NA


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