USART CFG addressOffset = 0x000

The CFG register contains communication and mode settings for aspects of the USART that would normally be configured once in an application.

Note: If software needs to change configuration values, the following sequence should be used: 1) Make sure the USART is not currently sending or receiving data. 2) Disable the USART by writing a 0 to the Enable bit (0 may be written to the entire register). 3) Write the new configuration value, with the ENABLE bit set to 1.
Table 1. USART registerName = CFG addressOffset = 0x000
Bit Symbol Value Description Reset Value
0 ENABLE   USART Enable. 0
    0 Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, all USART interrupts are disabled. When Enable is set again, CFG and most other control bits remain unchanged. For instance, when re-enabled, the USART will immediately generate a TxRdy interrupt (if enabled in the INTENSET register) because the transmitter has been reset and is therefore available.  
    1 Enabled. The USART is enabled for operation.  
1 -   Reserved. Read value is undefined, only zero should be written. NA
3:2 DATALEN   Selects the data size for the USART. 00
    0x0 7 bit Data length.  
    0x1 8 bit Data length.  
    0x2 9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTL register.  
    0x3 Reserved.  
5:4 PARITYSEL   Selects what type of parity is used by the USART. 00
    0x0 No parity.  
    0x1 Reserved.  
    0x2 Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, and the number of 1s in a received character is expected to be even.  
    0x3 Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, and the number of 1s in a received character is expected to be odd.  
6 STOPLEN   Number of stop bits appended to transmitted data. Only a single stop bit is required for received data. 0
    0 1 stop bit.  
    1 2 stop bits. This setting should only be used for asynchronous communication.  
7 -   Reserved. Only write 0 to this bit.  
8 -   Reserved. Read value is undefined, only zero should be written. NA
9 CTSEN   CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART’s own RTS if loopback mode is enabled. See USART Flow control for more information. 0
    0 No flow control. The transmitter does not receive any automatic flow control signal.  
    1 Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes.  
10 -   Reserved. Read value is undefined, only zero should be written. NA
11 SYNCEN   Selects synchronous or asynchronous operation. 0
    0 Asynchronous mode is selected.  
    1 Synchronous mode is selected.  
12 CLKPOL   Selects the clock polarity and sampling edge of received data in synchronous mode. 0
    0 Falling edge. Un_RXD is sampled on the falling edge of SCLK.  
    1 Rising edge. Un_RXD is sampled on the rising edge of SCLK.  
13 -   Reserved. Read value is undefined, only zero should be written. NA
14 SYNCMST   Synchronous mode Master select. 0
    0 Slave. When synchronous mode is enabled, the USART is a slave.  
    1 Master. When synchronous mode is enabled, the USART is a master.  
15 LOOP   Selects data loopback mode. 0
    0 Normal operation.  
    1 Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD and Un_RTS activity will also appear on external pins if these functions are configured to appear on device pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN.  
31:16 -   Reserved. Read value is undefined, only zero should be written. NA

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