|Registers / USART0/1/2 Register description|
The Baud Rate Generator is a simple 16-bit integer divider controlled by the BRG register. The BRG register contains the value used to divide the base clock in order to produce the clock used for USART internal operations.
A 16-bit value allows producing standard baud rates from 300 baud and lower at the highest frequency of the device, up to 921,600 baud from a base clock as low as 14.7456 MHz.
Typically, the baud rate clock is 16 times the actual baud rate. This overclocking allows for centering the data sampling time within a bit cell, and for noise reduction and detection by taking three samples of incoming data.
Details on how to select the right values for BRG can be found later in this chapter, see USART Clocking and Baud rates.
|15:0||BRGVAL||This value is used to divide the USART input clock to determine
the baud rate, based on the input clock from the FRG.
0 = The FRG clock is used directly by the USART function.
1 = The FRG clock is divided by 2 before use by the USART function.
2 = The FRG clock is divided by 3 before use by the USART function.
0xFFFF = The FRG clock is divided by 65,536 before use by the USART function.
|31:16||-||Reserved. Read value is undefined, only zero should be written.||NA|
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