USART Features

  • 7, 8, or 9 data bits and 1 or 2 stop bits
  • Synchronous mode with master or slave operation. Includes data phase selection and continuous clock option.
  • Multiprocessor/multidrop (9-bit) mode with software address compare. (RS-485 possible with software address detection and transceiver direction control.)
  • Parity generation and checking: odd, even, or none.
  • One transmit and one receive data buffer.
  • RTS/CTS for hardware signaling for automatic flow control. Software flow control can be performed using Delta CTS detect, Transmit Disable control, and any GPIO as an RTS output.
  • Received data and status can optionally be read from a single register
  • Break generation and detection.
  • Receive data is 2 of 3 sample "voting". Status flag set when one sample differs.
  • Built-in Baud Rate Generator.
  • A fractional rate divider is shared among all USARTs.
  • Interrupts available for Receiver Ready, Transmitter Ready, Receiver Idle, change in receiver break detect, Framing error, Parity error, Overrun, Underrun, Delta CTS detect, and receiver sample noise detected.
  • Loopback mode for testing of data and flow control.

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