All three USARTs use a common peripheral clock (U_PCLK) and, if
needed, a fractional baud rate generator. The peripheral clock and the fractional
divider for the baud rate calculation are set up in the SYSCON block as follows:
- Configure the UART clock by writing a value
UARTCLKDIV > 0 in the USART peripheral clock divider register. This
is the divided main clock common to all USARTs.
SYSCON UARTCLKDIV addressOffset = 0x094
- If a fractional value is needed to obtain a particular
baud rate, program the fractional divider. The fractional divider
value is the fraction of MULT/DIV. The MULT value is programmed
in the UARTFRGMULT register and the DIV value is programmed with the
fixed value of 256 in the UARTFRGDIV register in the SYSCON block.
U_PCLK = UARTCLKDIV/(1+(MULT/DIV))
The following rules apply for MULT and DIV:
- Always set DIV to 256 by programming
the UARTFRGDIV register with the value of 0xFF.
- Program any value between 0 and 255 in the UARTFRGMULT
SYSCON UARTFRGMULT addressOffset = 0x0F4
SYSCON UARTFRGDIV addressOffset = 0x0F0
- In asynchronous mode: Configure the baud rate divider
BRGVAL in the USARTn BRG register. The baud rate divider divides
the common USART peripheral clock by a factor of 16 multiplied by
the baud rate value to provide the
baud rate = U_PCLK/16 x BRGVAL.
USART BRG addressOffset = 0x020
- In synchronous mode: The serial clock is Un_SCLK = U_PCLK/BRGVAL.
For details on the clock configuration see:
USART Clocking and Baud rates