|Registers / SYSCON Register description|
All USART peripherals share a common clock U_PCLK, which can be adjusted by a fractional divider:
U_PCLK = UARTCLKDIV/(1 + MULT/DIV).
UARTCLKDIV is the USART clock configured in the UARTCLKDIV register.
The fractional portion (1 + MULT/DIV) is determined by the two USART fractional divider registers in the SYSCON block:
|7:0||MULT||Numerator of the fractional divider. MULT is equal to the programmed value.||0|
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