SYSCON UARTFRGMULT addressOffset = 0x0F4

All USART peripherals share a common clock U_PCLK, which can be adjusted by a fractional divider:

U_PCLK = UARTCLKDIV/(1 + MULT/DIV).

UARTCLKDIV is the USART clock configured in the UARTCLKDIV register.

The fractional portion (1 + MULT/DIV) is determined by the two USART fractional divider registers in the SYSCON block:

  1. The DIV denominator of the fractional divider value is programmed in the UARTFRGDIV register. See SYSCON registerName = UARTFRGDIV addressOffset = 0x0F0.
  2. The MULT value programmed in this register is the numerator of the fractional divider value used by the fractional rate generator to create the fractional component to the baud rate.

See also:

USART Configure the USART clock and baud rate

USART Clocking and Baud rates

Table 1. SYSCON USART fractional generator multiplier value register (UARTFRGMULT, address 0x4004 80F4) bit description
Bit Symbol Description Reset value
7:0 MULT Numerator of the fractional divider. MULT is equal to the programmed value. 0
31:8 - Reserved -

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