SYSCON UARTFRGDIV addressOffset = 0x0F0

All USART peripherals share a common clock U_PCLK, which can be adjusted by a fractional divider:

U_PCLK = UARTCLKDIV/(1 + MULT/DIV).

UARTCLKDIV is the USART clock configured in the UARTCLKDIV register.

The fractional portion (1 + MULT/DIV) is determined by the two USART fractional divider registers in the SYSCON block:

  1. The DIV value programmed in this register is the denominator of the divider used by the fractional rate generator to create the fractional component of U_PCLK.
  2. The MULT value of the fractional divider is programmed in the UARTFRGMULT register. See SYSCON USART fractional generator multiplier value register (UARTFRGMULT, address 0x4004 80F4) bit description.
Note: To use of the fractional baud rate generator, you must write 0xFF to this register to yield a denominator value of 256. All other values are not supported.

See also:

USART Configure the USART clock and baud rate

USART Clocking and Baud rates

Table 1. SYSCON registerName = UARTFRGDIV addressOffset = 0x0F0
Bit Symbol Description Reset value
7:0 DIV Denominator of the fractional divider. DIV is equal to the programmed value +1. Always set to 0xFF to use with the fractional baud rate generator. 0
31:8 - Reserved -

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