SYSCON SYSPLLCTRL addressOffset = 0x008

This register connects and enables the system PLL and configures the PLL multiplier and divider values. The PLL accepts an input frequency from 10 MHz to 25 MHz from various clock sources. The input frequency is multiplied to a higher frequency and then divided down to provide the actual clock used by the CPU, peripherals, and memories. The PLL can produce a clock up to the maximum allowed for the CPU.

Note: The divider values for P and M must be selected so that the PLL output clock frequency FCLKOUT is lower than 100 MHz.
Table 1. SYSCON registerName = SYSPLLCTRL addressOffset = 0x008
Bit Symbol Value Description Reset value
4:0 MSEL   Feedback divider value. The division value M is the programmed MSEL value + 1. 00000: Division ratio M = 1 to 11111: Division ratio M = 32 0
6:5 PSEL   Post divider ratio P. The division ratio is 2 × P. 0
    0x0 P = 1  
    0x1 P = 2  
    0x2 P = 4  
    0x3 P = 8  
31:7 - - Reserved. Do not write ones to reserved bits. -