|Registers / SYSCON Register description|
This register controls how the main clock is divided to provide the system clock to the core, memories, and the peripherals. The system clock can be shut down completely by setting the DIV field to zero.
|7:0||DIV||System AHB clock divider values 0: System clock disabled. 1: Divide by 1. to 255: Divide by 255.||0x01|
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