SYSCON SYSAHBCLKCTRL addressOffset = 0x080

The SYSAHBCLKCTRL register enables the clocks to individual system and peripheral blocks. The system clock (bit 0) provides the clock for the AHB, the APB bridge, the ARM Cortex-M0+, the SYSCON block, and the PMU. This clock cannot be disabled.

Table 1. SYSCON registerName = SYSAHBCLKCTRL addressOffset = 0x080
Bit Symbol Value Description Reset value
0 SYS   Enables the clock for the AHB, the APB bridge, the Cortex-M0+ core clocks, SYSCON, and the PMU. This bit is read only and always reads as 1. 1
    0 Reserved  
    1 Enable  
1 ROM   Enables clock for ROM. 1
    0 Disable  
    1 Enable  
2 RAM   Enables clock for SRAM. 1
    0 Disable  
    1 Enable  
3 FLASHREG   Enables clock for flash register interface. 1
    0 Disable  
    1 Enable  
4 FLASH   Enables clock for flash. 1
    0 Disable  
    1 Enable  
5 I2C   Enables clock for I2C. 0
    0 Disable  
    1 Enable  
6 GPIO   Enables clock for GPIO port registers and GPIO pin interrupt registers. 1
    0 Disable  
    1 Enable  
7 SWM   Enables clock for switch matrix. 1
    0 Disable  
    1 Enable  
8 SCT   Enables clock for state configurable timer. 0
    0 Disable  
    1 Enable  
9 WKT   Enables clock for self wake-up timer. 0
    0 Disable  
    1 Enable  
10 MRT   Enables clock for multi-rate timer.  
    0 Disable  
    1 Enable  
11 SPI0   Enables clock for SPI0. 0
    0 Disable  
    1 Enable  
12 SPI1   Enables clock for SPI1.  
    0 Disable  
    1 Enable  
13 CRC   Enables clock for CRC. 0
    0 Disable  
    1 Enable  
14 UART0   Enables clock for USART0. 0
    0 Disable  
    1 Enable  
15 UART1   Enables clock for USART1. 0
    0 Disable  
    1 Enable  
16 UART2   Enables clock for USART2. 0
    0 Disable  
    1 Enable  
17 WWDT   Enables clock for WWDT. 0
    0 Disable  
    1 Enable  
18 IOCON   Enables clock for IOCON block. 0
    0 Disable  
    1 Enable  
19 ACMP   Enables clock to analog comparator. 0
    0 Disable  
    1 Enable  
31:20 - - Reserved -

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