SYSCON PDSLEEPCFG addressOffset = 0x230

The bits in this register (BOD_PD and WDTOSC_OD) can be programmed to control aspects of Deep-sleep and Power-down modes. The bits are loaded into corresponding bits of the PDRUNCFG register when Deep-sleep mode or Power-down mode is entered.

Note: Hardware forces the analog blocks to be powered down in Deep-sleep and Power-down modes. An exception are the BOD and watchdog oscillator, which can be configured to remain running through this register. The WDTOSC_PD value written to the PDSLEEPCFG register is overwritten if the LOCK bit in the WWDT MOD register (see WWDT registerName = MOD addressOffset = 0x000) is set. See WWDT General description for details.
Table 1. SYSCON registerName = PDSLEEPCFG addressOffset = 0x230
Bit Symbol Value Description Reset value
2:0     Reserved. 0b111
3 BOD_PD   BOD power-down control for Deep-sleep and Power-down mode 1
    0 Powered  
    1 Powered down  
5:4     Reserved. 11
6 WDTOSC_PD   Watchdog oscillator power-down control for Deep-sleep and Power-down mode. Changing this bit to powered-down has no effect when the LOCK bit in the WWDT MOD register is set. In this case, the watchdog oscillator is always running. 1
    0 Powered  
    1 Powered down  
15:7 -   Reserved 0b111111111
31:16 - - Reserved 0

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