SYSCON PDRUNCFG addressOffset = 0x238

The PDRUNCFG register controls the power to the various analog blocks. This register can be written to at any time while the chip is running, and a write will take effect immediately with the exception of the power-down signal to the IRC.

To avoid glitches when powering down the IRC, the IRC clock is automatically switched off at a clean point. Therefore, for the IRC a delay is possible before the power-down state takes effect.

The system oscillator requires typically 500 μs to start up after the SYSOSC_PD bit has been changed from 1 to 0. There is no hardware flag to monitor the state of the system oscillator. Therefore, add a software delay of about 500 μs before using the system oscillator after power-up.

Table 1. SYSCON registerName = PDRUNCFG addressOffset = 0x238
Bit Symbol Value Description Reset value
0 IRCOUT_PD   IRC oscillator output power 0
    0 Powered  
    1 Powered down  
1 IRC_PD   IRC oscillator power down 0
    0 Powered  
    1 Powered down  
2 FLASH_PD   Flash power down 0
    0 Powered  
    1 Powered down  
3 BOD_PD   BOD power down 0
    0 Powered  
    1 Powered down  
4 -   Reserved. 1
5 SYSOSC_PD   Crystal oscillator power down. After power-up, add a software delay of approximately 500 μs before using. 1
    0 Powered  
    1 Powered down  
6 WDTOSC_PD   Watchdog oscillator power down. Changing this bit to powered-down has no effect when the LOCK bit in the WWDT MOD register is set. In this case, the watchdog oscillator is always running. 1
    0 Powered  
    1 Powered down  
7 SYSPLL_PD   System PLL power down 1
    0 Powered  
    1 Powered down  
11:8 -   Reserved. Always write these bits as 0b1101 0b1101
14:12 -   Reserved. Always write these bits as 0b110 0b110
15 ACMP   Analog comparator power down 1
    0 Powered  
    1 Powered down  
31:16 - - Reserved 0

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