SYSCON NMISRC addressOffset = 0x174

The NMI source selection register selects a peripheral interrupt as source for the NMI interrupt of the ARM Cortex-M0+ core. For a list of all peripheral interrupts and their IRQ numbers see NVIC Connection of interrupt sources to the NVIC. For a description of the NMI functionality, see NVIC General description.

Note: When you want to change the interrupt source for the NMI, you must first disable the NMI source by setting bit 31 in this register to 0. Then change the source by updating the IRQN bits and re-enable the NMI source by setting bit 31 to 1.
Table 1. SYSCON registerName = NMISRC addressOffset = 0x174
Bit Symbol Description Reset value
4:0 IRQN The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) if bit 31 is 1. See NVIC Connection of interrupt sources to the NVIC for the list of interrupt sources and their IRQ numbers. 0
30:5 - Reserved -
31 NMIEN Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by bits 4:0. 0
Note: If the NMISRC register is used to select an interrupt as the source of Non-Maskable interrupts, and the selected interrupt is enabled, one interrupt request can result in both a Non-Maskable and a normal interrupt. This can be avoided by disabling the normal interrupt in the NVIC.