|Registers / SYSCON Register description|
The NMI source selection register selects a peripheral interrupt as source for the NMI interrupt of the ARM Cortex-M0+ core. For a list of all peripheral interrupts and their IRQ numbers see NVIC Connection of interrupt sources to the NVIC. For a description of the NMI functionality, see NVIC General description.
|4:0||IRQN||The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) if bit 31 is 1. See NVIC Connection of interrupt sources to the NVIC for the list of interrupt sources and their IRQ numbers.||0|
|31||NMIEN||Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by bits 4:0.||0|
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