SYSCON IOCONCLKDIV addressOffset = 0x134

These registers individually configure the seven peripheral input clocks (IOCONFILTR_PCLK) to the IOCON programmable glitch filter. The clocks can be shut down by setting the DIV bits to 0x0.

Table 1. SYSCON registerName = IOCONCLKDIV[6:0] addressOffset = 0x134
Bit Symbol Description Reset value
7:0 DIV IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255. 0
31:8 - Reserved 0x00