|System control and clock configuration (SYSCON)|
System PLL block diagram
System PLL block diagram
The LPC81x uses the system PLL to create the clocks for the core and peripherals. The input frequency range is 10 MHz to 25 MHz. The input clock is fed directly to the Phase-Frequency Detector (PFD). This block compares the phase and frequency of its inputs, and generates a control signal when phase and/ or frequency do not match. The loop filter filters these control signals and drives the current controlled oscillator (CCO), which generates the main clock and optionally two additional phases. The CCO frequency range is 156 MHz to 320 MHz. These clocks are either divided by 2×P by the programmable post divider to create the output clocks, or are sent directly to the outputs. The main output clock is then divided by M by the programmable feedback divider to generate the feedback clock. The output signal of the phase-frequency detector is also monitored by the lock detector, to signal when the PLL has locked on to the input clock.
The lock detector measures the phase difference between the rising edges of the input and feedback clocks. Only when this difference is smaller than the so called “lock criterion” for more than eight consecutive input clock periods, the lock output switches from low to high. A single too large phase difference immediately resets the counter and causes the lock signal to drop (if it was high). Requiring eight phase measurements in a row to be below a certain figure ensures that the lock detector will not indicate lock until both the phase and frequency of the input and feedback clocks are very well aligned. This effectively prevents false lock indications, and thus ensures a glitch free lock signal.
To reduce the power consumption when the PLL clock is not needed, a PLL Power-down mode has been incorporated. This mode is enabled by setting the SYSPLL_PD bit to one in the Power-down configuration register (SYSCON registerName = PDRUNCFG addressOffset = 0x238). In this mode, the internal current reference will be turned off, the oscillator and the phase-frequency detector will be stopped and the dividers will enter a reset state. While in PLL Power-down mode, the lock output will be low to indicate that the PLL is not in lock. When the PLL Power-down mode is terminated by setting the SYSPLL_PD bit to zero, the PLL will resume its normal operation and will make the lock signal high once it has regained lock on the input clock.
The division ratio of the post divider is controlled by the PSEL bits. The division ratio is two times the value of P selected by PSEL bits as shown in SYSCON registerName = SYSPLLCTRL addressOffset = 0x008. This guarantees an output clock with a 50% duty cycle.
The feedback divider’s division ratio is controlled by the MSEL bits. The division ratio between the PLL’s output clock and the input clock is the decimal value on MSEL bits plus one, as specified in SYSCON registerName = SYSPLLCTRL addressOffset = 0x008.
Changing the divider ratio while the PLL is running is not recommended. As there is no way to synchronize the change of the MSEL and PSEL values with the dividers, the risk exists that the counter will read in an undefined value, which could lead to unwanted spikes or drops in the frequency of the output clock. The recommended way of changing between divider settings is to power down the PLL, adjust the divider settings and then let the PLL start up again.
The PLL frequency equations use the following parameters:
|FCLKIN||Frequency of sys_pllclkin (input clock to the system PLL) from the SYSPLLCLKSEL multiplexer (see SYSCON SYSPLLCLKSEL addressOffset = 0x040).|
|FCCO||Frequency of the Current Controlled Oscillator (CCO); 156 to 320 MHz.|
|FCLKOUT||Frequency of sys_pllclkout. This is the PLL output frequency and must be < 100 MHz.|
|P||System PLL post divider ratio; PSEL bits in SYSPLLCTRL (see SYSCON SYSPLLCTRL addressOffset = 0x008).|
|M||System PLL feedback divider register; MSEL bits in SYSPLLCTRL (see SYSCON SYSPLLCTRL addressOffset = 0x008).|
In this mode the post divider is enabled, giving a 50% duty cycle clock with the following frequency relations:
To select the appropriate values for M and P, it is recommended to follow these steps:
SYSCON PLL configuration examples shows how to configure the PLL for a 12 MHz crystal oscillator using the SYSPLLCTRL register (SYSCON registerName = SYSPLLCTRL addressOffset = 0x008). The main clock is equivalent to the system clock if the system clock divider SYSAHBCLKDIV is set to one (see SYSCON registerName = SYSAHBCLKDIV addressOffset = 0x078).
|PLL input clock sys_pllclkin (Fclkin)||Main clock (Fclkout)||MSEL bits SYSCON registerName = SYSPLLCTRL addressOffset = 0x008||M divider value||PSEL bits SYSCON registerName = SYSPLLCTRL addressOffset = 0x008||P divider value||FCCO frequency||SYSAHBCLKDIV||System clock|
|12 MHz||60 MHz||00100 (binary)||5||01 (binary)||2||240 MHz||2||30 MHz|
|12 MHz||24 MHz||00001(binary)||2||10 (binary)||4||192 MHz||1||24 MHz|
In this mode, the internal current reference will be turned off, the oscillator and the phase-frequency detector will be stopped and the dividers will enter a reset state. While in PLL Power-down mode, the lock output will be low, to indicate that the PLL is not in lock. When the PLL Power-down mode is terminated by SYSPLL_PD bit to zero in the Power-down configuration register (SYSCON registerName = PDRUNCFG addressOffset = 0x238), the PLL will resume its normal operation and will make the lock signal high once it has regained lock on the input clock.
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