SYSCON General description

Clock generation

The system control block generates all clocks for the chip. Only the low-power oscillator used for wake-up timing is controlled by the PMU. Except for the USART clock and the clock to configure the glitch filters of the digital I/O pins, the clocks to the core and peripherals run at the same frequency. The maximum system clock frequency is 30 MHz.

Note: The main clock frequency is limited to 100 MHz.
LPC81x clock generation

Power control of analog components

The system control block controls the power to the analog components such as the oscillators and PLL, the BOD, and the analog comparator. For details, see the following registers:

SYSCON PDSLEEPCFG addressOffset = 0x230

SYSCON SYSPLLCTRL addressOffset = 0x008

SYSCON WDTOSCCTRL addressOffset = 0x024

SYSCON SYSOSCCTRL addressOffset = 0x020

Configuration of reduced power-modes

The system control block configures analog blocks that can remain running in the reduced power modes (the BOD and the watchdog oscillator for safe operation) and enables various interrupts to wake up the chip when the internal clocks are shut down in Deep-sleep and Power-down modes. For details, see the following registers:

SYSCON PDRUNCFG addressOffset = 0x238

SYSCON STARTERP1 addressOffset = 0x214

Reset and interrupt control

The peripheral reset control register in the system control register allows to assert and release individual peripheral resets. See SYSCON registerName = PRESETCTRL addressOffset = 0x004.

Up to eight external pin interrupts can be assigned to any digital pin in the system control block (see SYSCON PINTSEL addressOffset = 0x178).