The clock source for the registers and memories is derived
from main clock. The main clock can be sourced from the IRC at a
fixed clock frequency of 12 MHz or from the PLL.
The divided main clock is called the system clock and
clocks the core, the memories, and the peripherals (register interfaces
and peripheral clocks).
- Select the main clock. You have the following
- IRC: 12 MHz internal oscillator (default).
- PLL output: You must configure the PLL to use the PLL
SYSCON MAINCLKSEL addressOffset = 0x070
- Update the main clock source.
SYSCON MAINCLKUEN addressOffset = 0x074
- Select the divider value for the system clock. A divider
value of 0 disables the system clock.
SYSCON SYSAHBCLKDIV addressOffset = 0x078
- Select the memories and peripherals that are operating
in your application and therefore must have an active clock. The
core is always clocked.
SYSCON SYSAHBCLKCTRL addressOffset = 0x080