SPI TXDATCTL addressOffset = 0x018

The TXDATCTL register provides a location where both transmit data and control information can be written simultaneously. This allows detailed control of the SPI without a separate write of control information for each piece of data.

Note: The SPI has no receiver control registers. Hence software needs to set the data length in the transmitter control or transmitter data and control register first in order to handle reception with correct data length. The programmed data length becomes active only when data is actually transmitted. Therefore, this must be done before any data can be received.

When control information remains static during transmit, the TXDAT register should be used (see SPI TXDAT addressOffset = 0x01C) instead of the TXDATCTL register. Control information can then be written separately via the TXCTL register (see SPI TXCTL addressOffset = 0x020). The upper part of TXDATCTL (bits 27 to 16) are the same bits contained in the TXCTL register. The two registers simply provide two ways to access them.

For details on the slave select process, see SPI Slave select.

For details on using multiple consecutive data transmits for data lengths larger than 16 bit, see SPI Data lengths greater than 16 bits.

For details on data stalls, see SPI Data stalls.

Table 1. SPI registerName = TXDATCTL addressOffset = 0x018
Bit Symbol Value Description Reset value
15:0 TXDAT   Transmit Data. This field provides from 1 to 16 bits of data to be transmitted. 0
16 TXSSEL_N   Transmit Slave Select. This field asserts SSEL in master mode. The output on the pin is active LOW by default.
Note: The active state of the SSEL pin is configured by bits in the CFG register.
0
    0 SSEL asserted.  
    1 SSEL not asserted.  
19:17 -   Reserved.  
20 EOT   End of Transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so for at least the time specified by the Transfer_delay value in the DLY register. When EOT is not set, data stalls can occur. When EOT is set, the transfer is completed and data stalls will not happen. 0
    0 SSEL not deasserted. This piece of data is not treated as the end of a transfer. SSEL will not be deasserted at the end of this data.  
    1 SSEL deasserted. This piece of data is treated as the end of a transfer. SSEL will be deasserted at the end of this piece of data.  
21 EOF   End of Frame. Between frames, a delay may be inserted, as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the FRAME_DELAY value = 0. This control can be used as part of the support for frame lengths greater than 16 bits. 0
    0 Data not EOF. This piece of data transmitted is not treated as the end of a frame.  
    1 Data EOF. This piece of data is treated as the end of a frame, causing the FRAME_DELAY time to be inserted before subsequent data is transmitted.  
22 RXIGNORE   Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver to simplify the transmit process. 0
    0 Read received data. Received data must be read in order to allow transmission to progress. In slave mode, an overrun error will occur if received data is not read before new data is received.  
    1 Ignore received data. Received data is ignored, allowing transmission without reading unneeded received data. No receiver flags are generated.  
23 -   Reserved. Read value is undefined, only zero should be written. NA
27:24 LEN   Data Length. Specifies the data length from 1 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits.

0x0 = Data transfer is 1 bit in length.

0x1 = Data transfer is 2 bits in length.

0x2 = Data transfer is 3 bits in length.

...

0xF = Data transfer is 16 bits in length.

0x0
31:28 -   Reserved. Read value is undefined, only zero should be written. NA


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