SPI0 Register and register bit mapping

Register Offset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
CFG 0x000 Enable   Master LSBF CPHA CPOL   Loop SPOL  
DLY 0x004 PRE_DELAY POST_DELAY FRAME_DELAY TRANSFER_DELAY  
STAT 0x008 RXRDY TXRDY RXOV TXUR SSA SSD STALLED ENDTRANSFER IDLE  
INTENSET 0x00C RXRDYEN TXRDYEN RXOVEN TXUREN SSAEN SSDEN  
INTENCLR 0x010 RXRDYEN TXRDYEN RXOVEN TXUREN SSAEN SSDEN  
RXDAT 0x014 RXDAT RXSSELN   SOT  
TXDATCTL 0x018 TXDAT TXSSELN   EOT EOF RXIGNORE   FLEN  
TXDAT 0x01C DATA  
TXCTL 0x020   TX_SSEL   EOT EOF RXIGNORE   FLEN  
DIV 0x024 DIVVAL  
INTSTAT 0x028 RXRDY TXRDY RXOV TXUR SSA SSD  

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