SPI Register description

The Reset Value reflects the data stored in used bits only. It does not include reserved bits content.

See CODE SPI Definitions for code examples that explain how to program the register interface.

Table 1. SPI Register overview: SPI (base address 0x4005 8000 (SPI0) and 0x4008 C000 (SPI1))
Name Access Offset Description Reset value Reference
CFG R/W 0x000 SPI Configuration register 0 SPI SPI Configuration register (CFG, addresses 0x4005 8000 (SPI0), 0x4005 C000 (SPI1)) bit description
DLY R/W 0x004 SPI Delay register 0 SPI registerName = DLY addressOffset = 0x004
STAT R/W 0x008 SPI Status. Some status flags can be cleared by writing a 1 to that bit position 0x0102 SPI registerName = STAT addressOffset = 0x008
INTENSET R/W 0x00C SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. 0 SPI registerName = INTENSET addressOffset = 0x00C
INTENCLR W 0x010 SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared. NA SPI registerName = INTENCLR addressOffset = 0x010
RXDAT R 0x014 SPI Receive Data NA SPI registerName = RXDAT addressOffset = 0x014
TXDATCTL R/W 0x018 SPI Transmit Data with Control 0 SPI registerName = TXDATCTL addressOffset = 0x018
TXDAT R/W 0x01C SPI Transmit Data 0 SPI registerName = TXDAT addressOffset = 0x01C
TXCTL R/W 0x020 SPI Transmit Control 0 SPI registerName = TXCTL addressOffset = 0x020
DIV R/W 0x024 SPI clock Divider 0 SPI registerName = DIV addressOffset = 0x024
INTSTAT R 0x028 SPI Interrupt Status 0x02 SPI SPI Interrupt Status register (INTSTAT, addresses 0x4005 8028 (SPI0) , 0x4005 C028 (SPI1)) bit description

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