SPI INTENSET addressOffset = 0x00C

The INTENSET register is used to enable various SPI interrupt sources. Enable bits in INTENSET are mapped in locations that correspond to the flags in the STAT register. The complete set of interrupt enables may be read from this register. Writing ones to implemented bits in this register causes those bits to be set. The INTENCLR register is used to clear bits in this register. See SPI registerName = STAT addressOffset = 0x008 for details of the interrupts.

Table 1. SPI registerName = INTENSET addressOffset = 0x00C
Bit Symbol Value Description Reset value
0 RXRDYEN   Determines whether an interrupt occurs when receiver data is available. 0
    0 No interrupt will be generated when receiver data is available.  
    1 An interrupt will be generated when receiver data is available in the RXDAT register.  
1 TXRDYEN   Determines whether an interrupt occurs when the transmitter holding register is available. 0
    0 No interrupt will be generated when the transmitter holding register is available.  
    1 An interrupt will be generated when data may be written to TXDAT.  
2 RXOVEN   Determines whether an interrupt occurs when a receiver overrun occurs. This happens in slave mode when there is a need for the receiver to move newly received data to the RXDAT register when it is already in use.

The interface prevents receiver overrun in Master mode by not allowing a new transmission to begin when a receiver overrun would otherwise occur.

0
    0 No interrupt will be generated when a receiver overrun occurs.  
    1 An interrupt will be generated if a receiver overrun occurs.  
3 TXUREN   Determines whether an interrupt occurs when a transmitter underrun occurs. This happens in slave mode when there is a need to transmit data when none is available. 0
    0 No interrupt will be generated when the transmitter underruns.  
    1 An interrupt will be generated if the transmitter underruns.  
4 SSAEN   Determines whether an interrupt occurs when the Slave Select is asserted. 0
    0 No interrupt will be generated when any Slave Select transitions from deasserted to asserted.  
    1 An interrupt will be generated when any Slave Select transitions from deasserted to asserted.  
5 SSDEN   Determines whether an interrupt occurs when the Slave Select is deasserted. 0
    0 No interrupt will be generated when all asserted Slave Selects transition to deasserted.  
    1 An interrupt will be generated when all asserted Slave Selects transition to deasserted.  
31:6 -   Reserved. Read value is undefined, only zero should be written. NA


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