SPI INTENCLR addressOffset = 0x010

The INTENCLR register is used to clear interrupt enable bits in the INTENSET register.

Table 1. SPI registerName = INTENCLR addressOffset = 0x010
Bit Symbol Description Reset value
0 RXRDYEN Writing 1 clears the corresponding bits in the INTENSET register. 0
1 TXRDYEN Writing 1 clears the corresponding bits in the INTENSET register. 0
2 RXOVEN Writing 1 clears the corresponding bits in the INTENSET register. 0
3 TXUREN Writing 1 clears the corresponding bits in the INTENSET register. 0
4 SSAEN Writing 1 clears the corresponding bits in the INTENSET register. 0
5 SSDEN Writing 1 clears the corresponding bits in the INTENSET register. 0
31:6 - Reserved. Read value is undefined, only zero should be written. NA

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