SPI DLY addressOffset = 0x004

The DLY register controls several programmable delays related to SPI signalling. These delays apply only to master mode, and are all stated in SPI clocks.

Timing details are shown in:

c-Framedelays.html#d17e1874__BGBFGCEC

c-Framedelays.html#d17e1874__BGBCIDDI

c-Framedelays.html#d17e1874__BGBIDFFA

Table 1. SPI registerName = DLY addressOffset = 0x004
Bit Symbol Description Reset value
3:0 PRE_DELAY Controls the amount of time between SSEL assertion and the beginning of a data transfer.

There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay.

0x0 = No additional time is inserted.

0x1 = 1 SPI clock time is inserted.

0x2 = 2 SPI clock times are inserted.

...

0xF = 15 SPI clock times are inserted.

0
7:4 POST_DELAY Controls the amount of time between the end of a data transfer and SSEL deassertion.

0x0 = No additional time is inserted.

0x1 = 1 SPI clock time is inserted.

0x2 = 2 SPI clock times are inserted.

...

0xF = 15 SPI clock times are inserted.

0
11:8 FRAME_DELAY If the EOF flag is set, controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT).

0x0 = No additional time is inserted.

0x1 = 1 SPI clock time is inserted.

0x2 = 2 SPI clock times are inserted.

...

0xF = 15 SPI clock times are inserted.

0
15:12 TRANSFER_DELAY Controls the minimum amount of time that the SSEL is deasserted between transfers.

0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.)

0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times.

0x2 = The minimum time that SSEL is deasserted is 3 SPI clock times.

...

0xF = The minimum time that SSEL is deasserted is 16 SPI clock times.

0
31:16 - Reserved. Read value is undefined, only zero should be written. NA


-->