|Registers / SPI0/1 Register description|
The DIV register determines the clock used by the SPI in master mode.
For details on clocking, see SPI Clocking and data rates.
|15:0||DIVVAL||Rate divider value. Specifies how the PCLK for the SPI is
divided to produce the SPI clock rate in master mode.
DIVVAL is -1 encoded such that the value 0 results in PCLK/1, the value 1 results in PCLK/2, up to the maximum possible divide value of 0xFFFF, which results in PCLK/65536.
|31:16||-||Reserved. Read value is undefined, only zero should be written.||NA|
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