SPI DIV addressOffset = 0x024

The DIV register determines the clock used by the SPI in master mode.

For details on clocking, see SPI Clocking and data rates.

Table 1. SPI registerName = DIV addressOffset = 0x024
Bit Symbol Description Reset Value
15:0 DIVVAL Rate divider value. Specifies how the PCLK for the SPI is divided to produce the SPI clock rate in master mode.

DIVVAL is -1 encoded such that the value 0 results in PCLK/1, the value 1 results in PCLK/2, up to the maximum possible divide value of 0xFFFF, which results in PCLK/65536.

31:16 - Reserved. Read value is undefined, only zero should be written. NA