|SPI0/1 / SPI General description|
Several delays can be specified for SPI frames. These include:
Pre_delay and Post_delay are illustrated by the examples in c-Framedelays.html#d17e1874__BGBDFDAH. The Pre_delay value controls the amount of time between SSEL being asserted and the beginning of the subsequent data frame. The Post_delay value controls the amount of time between the end of a data frame and the deassertion of SSEL.
Pre_delay and Post_delay timing
The Frame_delay value controls the amount of time at the end of each frame. This delay is inserted when the EOF bit = 1. Frame_delay is illustrated by the examples in c-Framedelays.html#d17e1874__BGBJCFGJ. Note that frame boundaries occur only where specified. This is because frame lengths can be any size, involving multiple data writes. See SPI Data lengths greater than 16 bits for more information.
The Transfer_delay value controls the minimum amount of time that SSEL is deasserted between transfers, because the EOT bit = 1. When Transfer_delay = 0, SSEL may be deasserted for a minimum of one SPI clock time. Transfer_delay is illustrated by the examples in c-Framedelays.html#d17e1874__BGBGGEGD.
© NXP N.V. 2014. All rights reserved.