|SPI0/1 / SPI General description|
In order to use the SPI, clocking details must be defined. This includes configuring the system clock and selection of the clock divider value in DIV. See c-Basicconfiguration.html#d17e27__BGBCGBFD.
The SPI interface is designed to operate asynchronously from any on-chip clocks, and without the need for overclocking.
In slave mode, this means that the SCK from the external master is used directly to run the transmit and receive shift registers and other logic.
In master mode, the SPI rate clock produced by the SPI clock divider is used directly as the outgoing SCK.
The SPI clock divider is an integer divider. The SPI in master mode can be set to run at the same speed as the selected PCLK, or at lower integer divide rates. The SPI rate will be = PCLK_SPIn / DIVVAL.
In slave mode, the clock is taken from the SCK input and the SPI clock divider is not used.
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