SPI Clock and phase selection

SPI interfaces typically allow configuration of clock phase and polarity. These are sometimes referred to as numbered SPI modes, as described in SPI SPI mode summary and shown in #d1e1769/BGBDFCDH. CPOL and CPHA are configured by bits in the CFG register.

Table 1. SPI SPI mode summary
CPOL CPHA SPI Mode Description SCK rest state SCK data change edge SCK data sample edge
0 0 0 The SPI captures serial data on the first clock transition of the transfer (when the clock changes away from the rest state). Data is changed on the following edge. low falling rising
0 1 1 The SPI changes serial data on the first clock transition of the transfer (when the clock changes away from the rest state). Data is captured on the following edge. low rising falling
1 0 2 Same as mode 0 with SCK inverted. high rising falling
1 1 3 Same as mode 1 with SCK inverted. high falling rising


Basic SPI operating modes


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