SCTimer/PWM RES addressOffset = 0x058

The registers OUTn_SETn (SCTimer/PWM OUT_SET addressOffset = 0x500) and OUTnCLRn (SCTimer/PWM OUT_CLR addressOffset = 0x504) allow both setting and clearing to be indicated for an output in the same clock cycle, even for the same event. This SCT conflict resolution register resolves this conflict.

To enable an event to toggle an output, set the OnRES value to 0x3 in this register, and set the event bits in both the Set and Clear registers.

Table 1. SCTimer/PWM registerName = RES addressOffset = 0x058
Bit Symbol Value Description Reset value
1:0 O0RES   Effect of simultaneous set and clear on output 0. 0
    0x0 No change.  
    0x1 Set output (or clear based on the SETCLR0 field).  
    0x2 Clear output (or set based on the SETCLR0 field).  
    0x3 Toggle output.  
3:2 O1RES   Effect of simultaneous set and clear on output 1. 0
    0x0 No change.  
    0x1 Set output (or clear based on the SETCLR1 field).  
    0x2 Clear output (or set based on the SETCLR1 field).  
    0x3 Toggle output.  
5:4 O2RES   Effect of simultaneous set and clear on output 2. 0
    0x0 No change.  
    0x1 Set output (or clear based on the SETCLR2 field).  
    0x2 Clear output n (or set based on the SETCLR2 field).  
    0x3 Toggle output.  
7:6 O3RES   Effect of simultaneous set and clear on output 3. 0
    0x0 No change.  
    0x1 Set output (or clear based on the SETCLR3 field).  
    0x2 Clear output (or set based on the SETCLR3 field).  
    0x3 Toggle output.  
31:8 - - Reserved -

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