SCTimer/PWM HALT addressOffset = 0x00C

If UNIFY = 1 in the CONFIG register, only the _L bits are used.

If UNIFY = 0 in the CONFIG register, this register can be written to as two registers HALT_L and HALT_H. Both the L and H registers can be read or written individually or in a single 32-bit read or write operation.

Note: Any event halting the counter disables its operation until software clears the HALT bit (or bits) in the CTRL register (SCTimer/PWM registerName = CTRL addressOffset = 0x004).
Table 1. SCTimer/PWM registerName = HALT addressOffset = 0x00C
Bit Symbol Description Reset value
5:0 HALTMSK_L If bit n is one, event n sets the HALT_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 5 = bit 5). 0
15:6 - Reserved. -
21:16 HALTMSK_H If bit n is one, event n sets the HALT_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 5 = bit 21). 0
31:22 - Reserved. -

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