|Registers / SCT Register description|
Each event has one associated SCT event state mask register that allow this event to happen in one or more states of the counter selected by the HEVENT bit in the corresponding EVn_CTRL register.
An event n is disabled when its EVn_STATE register contains all zeros, since it is masked regardless of the current state.
In simple applications that do not use states, write 0x01 to this register to enable an event. Since the state always remains at its reset value of 0, writing 0x01 permanently enables this event for the default state 0.
|0||STATEMASK0||If this bit is set to one, event n configured in the EVn_CTRL register (n
= 0 to 5) is enabled in state 0.
If this bit is 0, the event is disabled (masked) in state 0.
|1||STATEMASK1||If this bit is set to one, event n configured in the EVn_CTRL register (n
= 0 to 5) is enabled in state 1.
If this bit is 0, the event is disabled (masked) in state 1.
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