SCTimer/PWM EV_CTRL addressOffset = 0x304

This register defines the conditions for event n to occur, other than the state variable which is defined by the state mask register. Most events are associated with a particular counter (high, low, or unified), in which case the event can depend on a match to that register. The other possible ingredient of an event is a selected input or output signal.

When the UNIFY bit is 0, each event is associated with a particular counter by the HEVENT bit in its event control register. An event cannot occur when its related counter is halted nor when the current state is not enabled to cause the event as specified in its event mask register. An event is permanently disabled when its event state mask register contains all 0s.

An enabled event can be programmed to occur based on a selected input or output edge or level and/or based on its counter value matching a selected match register (STOP bit = 0). An event can be enabled by the event counter’s HALT bit and STATE register. In bi-directional mode, events can also be enabled based on the direction of count.

Each event can modify its counter STATE value. If more than one event associated with the same counter occurs in a given clock cycle, only the state change specified for the highest-numbered event among them takes place. Other actions dictated by any simultaneously occurring events all take place.

Table 1. SCTimer/PWM registerName = EV[0:5]_CTRL addressOffset = 0x304
Bit Symbol Value Description Reset value
3:0 MATCHSEL - Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running. 0
4 HEVENT   Select L/H counter. Do not set this bit if UNIFY = 1. 0
    0 L state. Selects the L state and the L match register selected by MATCHSEL.  
    1 H state. Selects the H state and the H match register selected by MATCHSEL.  
5 OUTSEL   Input/output select 0
    0 Input. Selects the inputs elected by IOSEL.  
    1 Output. Selects the outputs selected by IOSEL.  
9:6 IOSEL - Selects the input or output signal associated with this event (if any). Do not select an input in this register, if CLKMODE is 1x. In this case the clock input is an implicit ingredient of every event.

IOSEL = 0 selects pins CTIN_0 or CTOUT_0, ..., IOSEL = 3 selects pins CTIN_3 or CTOUT_3.

11:10 IOCOND   Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period . 0
    0x0 LOW  
    0x1 Rise  
    0x2 Fall  
    0x3 HIGH  
13:12 COMBMODE   Selects how the specified match and I/O condition are used and combined.  
    0x0 OR. The event occurs when either the specified match or I/O condition occurs.  
    0x1 MATCH. Uses the specified match only.  
    0x2 IO. Uses the specified I/O condition only.  
    0x3 AND. The event occurs when the specified match and I/O condition occur simultaneously.  
14 STATELD   This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state.  
    0 Add. STATEV value is added into STATE (the carry-out is ignored).  
    1 Load. STATEV value is loaded into STATE.  
19:15 STATEV   This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value.  

If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down.

If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value.

22:21 DIRECTION   Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.  
    0x0 Direction independent. This event is triggered regardless of the count direction.  
    0x1 Counting up. This event is triggered only during up-counting when BIDIR = 1.  
    0x2 Counting down. This event is triggered only during down-counting when BIDIR = 1.  
31:23 -   Reserved