SCTimer/PWM CTRL addressOffset = 0x004

If UNIFY = 1 in the CONFIG register, only the _L bits are used.

If UNIFY = 0 in the CONFIG register, this register can be written to as two registers CTRL_L and CTRL_H. Both the L and H registers can be read or written individually or in a single 32-bit read or write operation.

All bits in this register can be written to when the counter is stopped or halted. When the counter is running, the only bits that can be written are STOP or HALT. (Other bits can be written in a subsequent write after HALT is set to 1.)

Note: If CLKMODE = 0x3 is selected, wait at least 12 system clock cycles between a write access to the H, L or unified version of this register and the next write access. This restriction does not apply when writing to the HALT bit or bits and then writing to the CTRL register again to restart the counters - for example because software must update the MATCH register, which is only allowed when the counters are halted.
Table 1. SCTimer/PWM registerName = CTRL addressOffset = 0x004
Bit Symbol Value Description Reset value
0 DOWN_L - This bit is 1 when the L or unified counter is counting down. Hardware sets this bit when the counter limit is reached and BIDIR is 1. Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0. 0
1 STOP_L - When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events related to the counter can occur. If such an event matches the mask in the Start register, this bit is cleared and counting resumes. 0
2 HALT_L - When this bit is 1, the L or unified counter does not run and no events can occur. A reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. If you want to remove the halt condition and keep the SCT in the stop condition (not running), then you can change the halt and stop condition with one single write to this register.
Note: Once set, only software can clear this bit to restore counter operation.
1
3 CLRCTR_L - Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0. 0
4 BIDIR_L   L or unified counter direction select 0
    0 Up. The counter counts up to its limit condition, then is cleared to zero.  
    1 Bidirectional. The counter counts up to its limit, then counts down to a limit condition or to 0.  
12:5 PRE_L - Specifies the factor by which the SCT clock is prescaled to produce the L or unified counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1.
Note: Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value.
0
15:13 -   Reserved  
16 DOWN_H - This bit is 1 when the H counter is counting down. Hardware sets this bit when the counter limit is reached and BIDIR is 1. Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0. 0
17 STOP_H - When this bit is 1 and HALT is 0, the H counter does not run, but I/O events related to the counter can occur. If such an event matches the mask in the Start register, this bit is cleared and counting resumes. 0
18 HALT_H - When this bit is 1, the H counter does not run and no events can occur. A reset sets this bit. When the HALT_H bit is one, the STOP_H bit is cleared. If you want to remove the halt condition and keep the SCT in the stop condition (not running), then you can change the halt and stop condition with one single write to this register.
Note: Once set, this bit can only be cleared by software to restore counter operation.
1
19 CLRCTR_H - Writing a 1 to this bit clears the H counter. This bit always reads as 0. 0
20 BIDIR_H   Direction select 0
    0 Up. The H counter counts up to its limit condition, then is cleared to zero.  
    1 Bidirectional. The H counter counts up to its limit, then counts down to a limit condition or to 0.  
28:21 PRE_H - Specifies the factor by which the SCT clock is prescaled to produce the H counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRELH+1.
Note: Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value.
0
31:29 -   Reserved  

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