SCTimer/PWM CONFIG addressOffset = 0x000

This register configures the overall operation of the SCT. Write to this register before any other registers.

Table 1. SCTimer/PWM registerName = CONFIG addressOffset = 0x000
Bit Symbol Value Description Reset value
0 UNIFY   SCT operation 0
    0 16-bit. The SCT operates as two 16-bit counters named L and H.  
    1 32-bit. The SCT operates as a unified 32-bit counter.  
2:1 CLKMODE   SCT clock mode 0
    0x0 Bus clock. The bus clock clocks the SCT and prescalers.  
    0x1 Prescaled bus clock. The SCT clock is the bus clock, but the prescalers are enabled to count only when sampling of the input selected by the CKSEL field finds the selected edge. The minimum pulse width on the clock input is 1 bus clock period. This mode is the high-performance sampled-clock mode.  
    0x2 Input. The input selected by CKSEL clocks the SCT and prescalers. The input is synchronized to the bus clock and possibly inverted. The minimum pulse width on the clock input is 1 bus clock period. This mode is the low-power sampled-clock mode.  
    0x3 Reserved.  
6:3 CKSEL   SCT clock select. All other values are reserved. 0
    0x0 Input 0 rising edges.  
    0x1 Input 0 falling edges.  
    0x2 Input 1 rising edges.  
    0x3 Input 1 falling edges.  
    0x4 Input 2 rising edges.  
    0x5 Input 2 falling edges.  
    0x6 Input 3 rising edges.  
    0x7 Input 3 falling edges.  
7 NORELAOD_L - A 1 in this bit prevents the lower match registers from being reloaded from their respective reload registers. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set. 0
8 NORELOAD_H - A 1 in this bit prevents the higher match registers from being reloaded from their respective reload registers. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set. 0
16:9 INSYNC - Synchronization for input N (bit 9 = input 0, bit 10 = input 1,..., bit 16 = input 7). A 1 in one of these bits subjects the corresponding input to synchronization to the SCT clock, before it is used to create an event. If an input is synchronous to the SCT clock, keep its bit 0 for faster response.

When the CLKMODE field is 1x, the bit in this field, corresponding to the input selected by the CKSEL field, is not used.

1
17 AUTOLIMIT_L -

A one in this bit causes a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event.

As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in uni-directional mode or to change the direction of count in bi-directional mode.

Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set.

 
18 AUTOLIMIT_H -

A one in this bit will cause a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event.

As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in uni-directional mode or to change the direction of count in bi-directional mode.

Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set.

 
31:19 -   Reserved -

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