SCTimer/PWM SCT PWM Example

c-SCTPWMExample.html#d10e3794__BGBICGBE shows a simple application of the SCT using two sets of match events (EV0/1 and EV3/4) to set/clear SCT output 0. The timer is automatically reset whenever it reaches the MAT0 match value.

In the initial state 0, match event EV0 sets output 0 to HIGH and match event EV1 clears output 0. The SCT input 0 is monitored: If input0 is found LOW by the next time the timer is reset(EV2), the state is changed to state 1, and EV3/4 are enabled, which create the same output but triggered by different match values. If input 0 is found HIGH by the next time the timer is reset, the associated event (EV5) causes the state to change back to state 0where the events EV0 and EV1 are enabled.

The example uses the following SCT configuration:

  • 1 input
  • 1 output
  • 5 match registers
  • 6 events and match 0 used with autolimit function
  • 2 states


SCT configuration example

This application of the SCT uses the following configuration (all register values not listed in SCTimer/PWM SCT configuration example are set to their default values):

Table 1. SCTimer/PWM SCT configuration example
Configuration Registers Setting
Counter CONFIG Uses one counter (UNIFY = 1).
CONFIG Enable the autolimit for MAT0. (AUTOLIMIT = 1.)
CTRL Uses unidirectional counter (BIDIR_L = 0).
Clock base CONFIG Uses default values for clock configuration.
Match/Capture registers REGMODE Configure one match register for each match event by setting REGMODE_L bits 0,1, 2, 3, 4 to 0. This is the default.
Define match values MATCH0/1/2/3/4 Set a match value MATCH0/1/2/4/5_L in each register. The match 0 register serves as an automatic limit event that resets the counter. without using an event. To enable the automatic limit, set the AUTOLIMIT bit in the CONFIG register.
Define match reload values MATCHREL0/1/2/3/4 Set a match reload value RELOAD0/1/2/3/4_L in each register (same as the match value in this example).
Define when event 0 occurs EV0_CTRL
  • Set COMBMODE = 0x1. Event 0 uses match condition only.
  • Set MATCHSEL = 1. Select match value of match register 1. The match value of MAT1 is associated with event 0.
Define when event 1 occurs EV1_CTRL
  • Set COMBMODE = 0x1. Event 1 uses match condition only.
  • Set MATCHSEL = 2 Select match value of match register 2. The match value of MAT2 is associated with event 1.
Define when event 2 occurs EV2_CTRL
  • Set COMBMODE = 0x3. Event 2 uses match condition and I/O condition.
  • Set IOSEL = 0. Select input 0.
  • Set IOCOND = 0x0. Input 0 is LOW.
  • Set MATCHSEL = 0. Chooses match register 0 to qualify the event.
Define how event 2 changes the state EV2_CTRL Set STATEV bits to 1 and the STATED bit to 1. Event 2 changes the state to state 1.
Define when event 3 occurs EV3_CTRL
  • Set COMBMODE = 0x1. Event 3 uses match condition only.
  • Set MATCHSEL = 0x3. Select match value of match register 3. The match value of MAT3 is associated with event 3..
Define when event 4 occurs EV4_CTRL
  • Set COMBMODE = 0x1. Event 4 uses match condition only.
  • Set MATCHSEL = 0x4. Select match value of match register 4.The match value of MAT4 is associated with event 4.
Define when event 5 occurs EV5_CTRL
  • Set COMBMODE = 0x3. Event 5 uses match condition and I/O condition.
  • Set IOSEL = 0. Select input 0.
  • Set IOCOND = 0x3. Input 0 is HIGH.
  • Set MATCHSEL = 0. Chooses match register 0 to qualify the event.
Define how event 5 changes the state EV5_CTRL Set STATEV bits to 0 and the STATED bit to 1. Event 5 changes the state to state 0.
Define by which events output 0 is set OUT0_SET Set SET0 bits 0 (for event 0) and 3 (for event 3) to one to set the output when these events 0 and 3 occur.
Define by which events output 0 is cleared OUT0_CLR Set CLR0 bits 1 (for events 1) and 4 (for event 4) to one to clear the output when events 1 and 4 occur.
Configure states in which event 0 is enabled EV0_STATE Set STATEMSK0 bit 0 to 1. Set all other bits to 0. Event 0 is enabled in state 0.
Configure states in which event 1 is enabled EV1_STATE Set STATEMSK1 bit 0 to 1. Set all other bits to 0. Event 1 is enabled in state 0.
Configure states in which event 2 is enabled EV2_STATE Set STATEMSK2 bit 0 to 1. Set all other bits to 0. Event 2 is enabled in state 0.
Configure states in which event 3 is enabled EV3_STATE Set STATEMSK3 bit 1 to 1. Set all other bits to 0. Event 3 is enabled in state 1.
Configure states in which event 4 is enabled EV4_STATE Set STATEMSK4 bit 1 to 1. Set all other bits to 0. Event 4 is enabled in state 1.
Configure states in which event 5 is enabled EV5_STATE Set STATEMSK5 bit 1 to 1. Set all other bits to 0. Event 5 is enabled in state 1.

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