SCTimer/PWM Match vs. I/O events

Counter operation is complicated by the prescaler and by clock mode 01 in which the SCT clock is the bus clock. However, the prescaler and counter are enabled to count only when a selected edge is detected on a clock input.

  • The prescaler is enabled when the clock mode is not 01, or when the input edge selected by the CLKSEL field is detected.
  • The counter is enabled when the prescaler is enabled, and (PRELIM=0 or the prescaler is equal to the value in PRELIM).

An I/O component of an event can occur in any SCT clock when its counter HALT bit is 0. In general, a Match component of an event can only occur in a UT clock when its counter HALT and STOP bits are both 0 and the counter is enabled.

SCTimer/PWM Event conditions shows when the various kinds of events can occur.

Table 1. SCTimer/PWM Event conditions
COMBMODE IOMODE Event can occur on clock:
IO Any Event can occur whenever HALT = 0 (type A).
MATCH Any Event can occur when HALT = 0 and STOP = 0 and the counter is enabled (type C).
OR Any From the IO component: Event can occur whenever HALT = 0 (A). From the match component: Event can occur when HALT = 0 and STOP = 0 and the counter is enabled (C).
AND LOW or HIGH Event can occur when HALT = 0 and STOP = 0 and the counter is enabled (C).
AND RISE or FALL Event can occur whenever HALT = 0 (A).

-->