SCTimer/PWM General description

The State Configurable Timer (SCT) allows a wide variety of timing, counting, output modulation, and input capture operations.

The most basic user-programmable option is whether a SCT operates as two 16-bit counters or a unified 32-bit counter. In the two-counter case, in addition to the counter value the following operational elements are independent for each half:

  • State variable
  • Limit, halt, stop, and start conditions
  • Values of Match/Capture registers, plus reload or capture control values

In the two-counter case, the following operational elements are global to the SCT:

  • Clock selection
  • Inputs
  • Events
  • Outputs
  • Interrupts

Events, outputs, and interrupts can use match conditions from either counter.

Note: In this chapter, the term bus error indicates an SCT response that makes the processor take an exception.

SCTimer/PWM block diagram

SCTimer/PWM counter and select logic