SCTimer/PWM Features

  • Two 16-bit counters or one 32-bit counter.
  • Counters clocked by bus clock or selected input.
  • Up counters or up-down counters.
  • State variable allows sequencing across multiple counter cycles.
  • The following conditions define an event: a counter match condition, an input (or output) condition, a combination of a match and/or and input/output condition in a specified state, and the count direction.
  • Events control outputs, interrupts, and the SCTimer states.
    • Match register 0 can be used as an automatic limit.
    • In bi-directional mode, events can be enabled based on the count direction.
    • Match events can be held until another qualifying event occurs.
  • Selected events can limit, halt, start, or stop a counter.
  • Supports:
    • 4 inputs
    • 4 outputs
    • 5 match/capture registers
    • 6 events
    • 2 states

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