Power profiles API Clock control

Invalid frequency (device maximum clock rate exceeded)

command[0] = 12000;-->
command[1] = 60000;-->
command[2] = CPU_FREQ_EQU;-->
command[3] = 0;-->
LPC_PWRD_API->set_pll(command, result);-->

The above code specifies a 12 MHz PLL input clock and a system clock of exactly 60 MHz. The application was ready to infinitely wait for the PLL to lock. But the expected system clock of 60 MHz exceeds the maximum of 30 MHz. Therefore set_pll returns PLL_INVALID_FREQ in result[0] and 12 000 in result[1] without changing the PLL settings.

Invalid frequency selection (system clock divider restrictions)

command[0] = 12000;-->
command[1] = 40;-->
command[2] = CPU_FREQ_LTE;-->
command[3] = 0;-->
LPC_PWRD_API->set_pll(command, result);-->

The above code specifies a 12 MHz PLL input clock, a system clock of no more than 40 kHz and no time-out while waiting for the PLL to lock. Since the maximum divider value for the system clock is 255 and running at 40 kHz would need a divide by value of 300, set_pll returns PLL_INVALID_FREQ in result[0] and 12 000 in result[1] without changing the PLL settings.

Exact solution cannot be found (PLL)

command[0] = 12000;-->
command[1] = 25000;-->
command[2] = CPU_FREQ_EQU;-->
command[3] = 0;-->
LPC_PWRD_API->set_pll(command, result);-->

The above code specifies a 12 MHz PLL input clock and a system clock of exactly 25 MHz. The application was ready to infinitely wait for the PLL to lock. Since there is no valid PLL setup within earlier mentioned restrictions, set_pll returns PLL_FREQ_NOT_FOUND in result[0] and 12 000 in result[1] without changing the PLL settings.

System clock less than or equal to the expected value

command[0] = 12000;-->
command[1] = 25000;-->
command[2] = CPU_FREQ_LTE;-->
command[3] = 0;-->
LPC_PWRD_API->set_pll(command, result);-->

The above code specifies a 12 MHz PLL input clock, a system clock of no more than 25 MHz and no locking time-out. set_pll returns PLL_CMD_SUCCESS in result[0] and 24000 in result[1]. The new system clock is 24 MHz.

System clock greater than or equal to the expected value

command[0] = 12000;-->
command[1] = 20000;-->
command[2] = CPU_FREQ_GTE;-->
command[3] = 0;-->
LPC_PWRD_API->set_pll(command, result);-->

The above code specifies a 12 MHz PLL input clock, a system clock of at least 20 MHz and no locking time-out. set_pll returns PLL_CMD_SUCCESS in result[0] and 24 000 in result[1]. The new system clock is 24 MHz.

System clock approximately equal to the expected value

command[0] = 12000;-->
command[1] = 16500;-->
command[2] = CPU_FREQ_APPROX;-->
command[3] = 0;-->
LPC_PWRD_API->set_pll(command, result);-->

The above code specifies a 12 MHz PLL input clock, a system clock of approximately 16.5 MHz and no locking time-out. set_pll returns PLL_CMD_SUCCESS in result[0] and 16 000 in result[1]. The new system clock is 16 MHz.


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