PMU PCON addressOffset = 0x000

The power control register selects whether one of the ARM Cortex-M0+ controlled power-down modes (Sleep mode or Deep-sleep/Power-down mode) or the Deep power-down mode is entered and provides the flags for Sleep or Deep-sleep/Power-down modes and Deep power-down modes respectively.

Table 1. PMU registerName = PCON addressOffset = 0x000
Bit Symbol Value Description Reset value
2:0 PM   Power mode 000
    0x0 Default. The part is in active or sleep mode.  
    0x1 Deep-sleep mode. ARM WFI will enter Deep-sleep mode.  
    0x2 Power-down mode. ARM WFI will enter Power-down mode.  
    0x3 Deep power-down mode. ARM WFI will enter Deep-power down mode (ARM Cortex-M0+ core powered-down).  
3 NODPD   A 1 in this bit prevents entry to Deep power-down mode when 0x3 is written to the PM field above, the SLEEPDEEP bit is set, and a WFI is executed. This bit is cleared only by power-on reset, so writing a one to this bit locks the part in a mode in which Deep power-down mode is blocked. 0
7:4 - - Reserved. Do not write ones to this bit. 0
8 SLEEPFLAG   Sleep mode flag 0
    0 Active mode. Read: No power-down mode entered. Part is in Active mode. Write: No effect.  
    1 Low power mode. Read: Sleep, Deep-sleep or Power-down mode entered. Write: Writing a 1 clears the SLEEPFLAG bit to 0.  
10:9 - - Reserved. Do not write ones to this bit. 0
11 DPDFLAG   Deep power-down flag 0
    0 Not Deep power-down. Read: Deep power-down mode not entered. Write: No effect. 0
    1 Deep power-down. Read: Deep power-down mode entered. Write: Clear the Deep power-down flag.  
31:12 - - Reserved. Do not write ones to this bit. 0

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