PMU DPDCTRL addressOffset = 0x014

The Deep power-down control register controls the low-power oscillator that can be used by the self wake-up timer to wake up from Deep power-down mode. In addition, this register configures the functionality of the WAKEUP pin (pin PIO0_4).

The bits in the register not used for deep power-down control (bits 31:4) can be used for storing additional data which are retained in Deep power-down mode in the same way as registers GPREG0 to GPREG3.

Note: If there is a possibility that the external voltage applied on pin V_ DD drops below 2.2 V during Deep power-down, the hysteresis of the WAKEUP input pin has to be disabled in this register before entering Deep power-down mode in order for the chip to wake up.
Note: Enabling the low-power oscillator in Deep power-down mode increases the power consumption. Only enable this oscillator if you need the self wake-up timer to wake up the part from Deep power-down mode. You may need the self wake-up timer if the wake-up pin is used for other purposes and the wake-up function is not available.
Table 1. PMU registerName = DPDCTRL addressOffset = 0x014
Bit Symbol Value Description Reset value
0 WAKEUPHYS   WAKEUP pin hysteresis enable 0
    0 Disabled. Hysteresis for WAKEUP pin disabled.  
    1 Enabled. Hysteresis for WAKEUP pin enabled.  
1 WAKEPAD_ DISABLE   WAKEUP pin disable. Setting this bit disables the wake-up pin, so it can be used for other purposes.
Note: Never set this bit if you intend to use a pin to wake up the part from Deep power-down mode. You can only disable the wake-up pin if the self wake-up timer is enabled and configured.
Note: Setting this bit is not necessary if Deep power-down mode is not used.
0
    0 Enabled. The wake-up function is enabled on pin PIO0_4.  
    1 Disabled. Setting this bit disables the wake-up function on pin PIO0_4.  
2 LPOSCEN   Enable the low-power oscillator for use with the 10 kHz self wake-up timer clock. You must set this bit if the CLKSEL bit in the self wake-up timer CTRL bit is set.

Do not enable the low-power oscillator if the self wake-up timer is clocked by the divided IRC.

0
    0 Disabled.  
    1 Enabled.  
3 LPOSCDPDEN   Enable the low-power oscillator in Deep power-down mode. Setting this bit causes the low-power oscillator to remain running during Deep power-down mode provided that bit 2 in this register is set as well.

You must set this bit for the self wake-up timer to be able to wake up the part from Deep power-down mode.

Note: Do not set this bit unless you use the self wake-up timer to wake up from Deep power-down mode.
0
    0 Disabled.  
    1 Enabled.  
31:4 -   Data retained during Deep power-down mode. 0x0

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