|Power Monitor Unit (PMU) / PMU Power management|
In Power-down mode, the system clock to the processor is disabled as in Sleep mode. All analog blocks are powered down, except for the BOD circuit and the watchdog oscillator, which must be selected or deselected during Power-down mode in the PDSLEEPCFG register. The main clock and therefore all peripheral clocks are disabled except for the clock to the watchdog timer if the watchdog oscillator is selected. The IRC itself and the flash are powered down, decreasing power consumption compared to Deep-sleep mode.
Power-down mode eliminates all power used by analog peripherals and all dynamic power used by the processor itself, memory systems and related controllers, and internal buses. The processor state and registers, peripheral registers, and internal SRAM values are maintained, and the logic levels of the pins remain static. Wake-up times are longer compared to the Deep-sleep mode.
Power consumption in Power-down mode can be configured by the power configuration setting in the PDSLEEPCFG (SYSCON registerName = PDSLEEPCFG addressOffset = 0x230) register in the same way as for Deep-sleep mode (see Power configuration in Deep-sleep mode):
The following steps must be performed to enter Power-down mode:
The microcontroller can wake up from Power-down mode in the same way as from Deep-sleep mode:
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