PMU Low power modes in the ARM Cortex-M0+ core

Entering and exiting the low power modes is always controlled by the ARM Cortex-M0+ core. The SCR register is the software interface for controlling the core’s actions when entering a low power mode. The SCR register is located on the ARM private peripheral bus.

PMU System control register

The System control register (SCR) controls entry to and exit from a low power state. This register is located on the private peripheral bus and is a R/W register with reset value of 0x0000 0000. The SCR register allows to put the ARM core into sleep mode or the entire system in Deep-sleep or Power-down mode. To set the low power state with SLEEPDEEP = 1 to either deep-sleep or power-down or to enter the Deep power-down mode, use the PCON register (PMU registerName = PCON addressOffset = 0x000).

Table 1. PMU registerName = SCR addressOffset = 0xD10
Bit Symbol Description Reset value
0 - Reserved. 0

Indicates sleep-on-exit when returning from Handler mode to Thread mode:

0 = do not sleep when returning to Thread mode.

1 = enter sleep, or deep sleep, on return from an ISR to Thread mode.

Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application.


Controls whether the processor uses sleep or deep-sleep as its low power mode:

0 = sleep

1 = deep sleep.

3 - Reserved. 0

Send Event on Pending bit:

0 = only enabled interrupts or events can wake-up the processor, disabled interrupts are excluded1 = enabled events and all interrupts, including disabled interrupts, can wake up the processor.

When an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE.

The processor also wakes up on execution of an
31:5 - Reserved. 0