|Power Monitor Unit (PMU)|
Power on the LPC81x is controlled by the PMU, by the SYSCON block, and the ARM Cortex-M0+ core. The following reduced power modes are supported in order from highest to lowest power consumption:
The sleep mode affects the ARM Cortex-M0+ core only. Peripherals and memories are active.
The Deep-sleep and power-down modes affect the core and the entire system with memories and peripherals. Before entering deep-sleep or power-down, you must switch the main clock to the IRC to provide a clock signal that can be shut down cleanly.
For maximal power savings, the entire system is shut down except for the general purpose registers in the PMU and the self wake-up timer. Only the general purpose registers in the PMU maintain their internal states. The part can wake up on a pulse on the WAKEUP pin or when the self wake-up timer times out. On wake-up, the part reboots.
If the part receives a wake-up signal in any of the reduced power modes, it wakes up to the active mode.
See these links for related registers and wake-up instructions:
To enable external or internal signals to wake up the part from Deep-sleep or Power-down modes: SYSCON registerName = STARTERP1 addressOffset = 0x214
To configure the USART to wake up the part: USART Configure the USART for wake-up
|Power mode||Wake-up source||Conditions|
|Sleep||Any interrupt||Enable interrupt in NVIC.|
|Deep-sleep and Power-down||Pin interrupts||
Enable pin interrupts in NVIC and STARTERP0 registers.
|Self Wake-up Timer (WKT) time-out||
|Interrupt from USART/SPI/I2C peripheral||
|Deep power-down||WAKEUP pin PIO0_4||Enable the WAKEUP function in the DPDCTRL register in the PMU.|
© NXP N.V. 2014. All rights reserved.