PMU General description

Power on the LPC81x is controlled by the PMU, by the SYSCON block, and the ARM Cortex-M0+ core. The following reduced power modes are supported in order from highest to lowest power consumption:

  1. Sleep mode:

    The sleep mode affects the ARM Cortex-M0+ core only. Peripherals and memories are active.

  2. Deep-sleep and power-down modes:

    The Deep-sleep and power-down modes affect the core and the entire system with memories and peripherals. Before entering deep-sleep or power-down, you must switch the main clock to the IRC to provide a clock signal that can be shut down cleanly.

    1. In Deep-sleep mode, the peripherals receive no internal clocks. The flash is in stand-by mode. The SRAM memory and all peripheral registers as well as the processor maintain their internal states. The WWDT, WKT, and BOD can remain active to wake up the system on an interrupt.
    2. In Power-down mode, the peripherals receive no internal clocks. The internal SRAM memory and all peripheral registers as well as the processor maintain their internal states. The flash memory is powered down. The WWDT, WKT, and BOD can remain active to wake up the system on an interrupt.
  3. Deep power-down mode:

    For maximal power savings, the entire system is shut down except for the general purpose registers in the PMU and the self wake-up timer. Only the general purpose registers in the PMU maintain their internal states. The part can wake up on a pulse on the WAKEUP pin or when the self wake-up timer times out. On wake-up, the part reboots.

Note: The LPC81x is in active mode when it is fully powered and operational after booting.

Wake-up process

If the part receives a wake-up signal in any of the reduced power modes, it wakes up to the active mode.

See these links for related registers and wake-up instructions:

Table 1. PMU Wake-up sources for reduced power modes
Power mode Wake-up source Conditions
Sleep Any interrupt Enable interrupt in NVIC.
Deep-sleep and Power-down Pin interrupts

Enable pin interrupts in NVIC and STARTERP0 registers.

  BOD interrupt
  • Enable interrupt in NVIC and STARTERP1 registers.
  • Enable interrupt in BODCTRL register.
  • BOD powered in PDSLEEPCFG register.
  BOD reset
  • Enable reset in BODCTRL register.
  • BOD powered in PDSLEEPCFG register.
  WWDT interrupt
  • Enable interrupt in NVIC and STARTERP1 registers.
  • WWDT running. Enable WWDT in WWDT MOD register and feed.
  • Enable interrupt in WWDT MOD register.
  • WDOsc powered in PDSLEEPCFG register.
  WWDT reset
  • WWDT running.
  • Enable reset in WWDT MOD register.
  • WDOsc powered in PDSLEEPCFG register.
  Self Wake-up Timer (WKT) time-out
  • Enable interrupt in NVIC and STARTERP1 registers.
  • Enable low-power oscillator in the DPDCTRL register in the PCON block.
  • Select low-power clock for WKT clock in the WKT CTRL register.
  • Start the WKT by writing a time-out value to the WKT COUNT register.
  Interrupt from USART/SPI/I2C peripheral
  • Enable interrupt in NVIC and STARTERP1 registers.
  • Enable USART/I2C/SPI interrupts.
  • Provide an external clock signal to the peripheral.
  • Configure the USART in synchronous slave mode and I2C and SPI in slave mode.
Deep power-down WAKEUP pin PIO0_4 Enable the WAKEUP function in the DPDCTRL register in the PMU.
  WKT time-out
  • Enable the low-power oscillator in the DPDCTRL register in the PMU.
  • Enable the low-power oscillator to keep running in Deep power-down mode in the DPDCTRL register in the PMU.
  • Select low-power clock for WKT clock in the WKT CTRL register.
  • Start WKT by writing a time-out value to the WKT COUNT register.

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