PINT SIENR addressOffset = 0x008

For each of the 8 pin interrupts selected in the PINTSELn registers (see SYSCON PINTSEL addressOffset = 0x178), one bit in the SIENR register sets the corresponding bit in the IENR register depending on the pin interrupt mode configured in the ISEL register:

  • If the pin interrupt mode is edge sensitive (PMODE = 0), the rising edge interrupt is set.
  • If the pin interrupt mode is level sensitive (PMODE = 1), the level interrupt is set.
Table 1. PINT registerName = SIENR addressOffset = 0x008
Bit Symbol Description Reset value Access
7:0 SETENRL Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt. NA WO
31:8 - Reserved. - -