PINT SIENF addressOffset = 0x014

For each of the 8 pin interrupts selected in the PINTSELn registers (see SYSCON PINTSEL addressOffset = 0x178), one bit in the SIENF register sets the corresponding bit in the IENF register depending on the pin interrupt mode configured in the ISEL register:

  • If the pin interrupt mode is edge sensitive (PMODE = 0), the falling edge interrupt is set.
  • If the pin interrupt mode is level sensitive (PMODE = 1), the HIGH-active interrupt is selected.
Table 1. PINT registerName = SIENF addressOffset = 0x014
Bit Symbol Description Reset value Access
7:0 SETENAF Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt. NA WO
31:8 - Reserved. - -